Impulse analyzer for time division multiplex switching systems



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IMPULSE ANALYZER FOR TIME DIVISION MULTIPLEX SWITCI-IING SYSTEMS Filed March 30, 1961 3 Sheets-Sheet 2 CONTROL STORAGE CALLING LINE STORE f CALLING DATA I /306 GEN.

I 'LV 'TI I I I I IDLM 338) IL I I I T g I I I oN-DFF HooK GATE I I 6 33' I I 343 ERASE HOOK STATE DETECTOR 2 OFF-ON HOOK GATE 337 END oF DIGIT GATE 353 -U- STEERING PULSE OUTPUT ON END OF DIGIT TO CONTROL STORAGE STORE 3 Sheets-Sheet 3 IMPULSE 332 GATE r 'LI loops/loo M sec.

1 l l l 1 l l l l FlNAx. oN HooK GATE 36| TIME PULSE GEN. loops/4M SEC. L f' i F. BARTLETT AVU- B VL

W. IMPULSE ANALYZER FOR TIME DIVISION MULTIPLI-BX SWITCHING SYSTEMS DELAY LINE MODULE (BLM) CONTROL STORAGE DELAY lOO )l S 8: STORE IMPULSE COUNTER SAMPLING Nov. Z4, 1964 Filed March 30, 1961 TO CALLING LINE STORE United States Patent O The present invention relates to impulse analyzers utilized in time division multiplex switching systems.

ln high speed time division multiplex switching systems, a pluralty of line circuits, each oi which is associated with a telephone subset or with a data handling device, are coupled to a common transmission highway through line gates. Where a iirst line circuit is to be coupled to a second line circuit through a common transmission highway, a repetitive pulse or time slot is assigned to the connection, the time slot being utilized to simultaneously actuate the line gates associated with the line circuits so that each line circuit is simultaneously coupled to a common transmission highway once during each repetitive transmission trame. This sampling process results in the transmission ot intelligence between the connected linecircuits. Where'the time divisionmultipleit switching system is a telephone exchange, a subscriber associated with the iirst vline circuit transmits intelligence to an impulse analyzer, which intelligence may be representative or on-hoolr, oft-hook, and directive information. This information is analyzed and utilized for control purposes. Prior art analyzers of this type have been relatively complicated and expensive.

Accordingly, it is a principal object of the present invention to provide a new and improved impulse analyzer for high speed time division multiplex electronic switching systems.

lt is a further object of the present invention to proide an inproved impulse analyzer which utilizes a minimum number of components, thereby totsharply reduce the cost of the analyzer.

lt is yet a further object of the present invention to provide a new and improved impulse analyzer for detecting various types oi cti-hook conditions, such as interdigit periods, periods between dial impulses of a particular digLOn-hoolc periods, such as dial impulses, and final on-hooh, and also for forwarding control signals to common control circuitry indicative of these various conditions.

lt is a feature of the present invention to provide an Vimgmlse analyzer comprising a single two-stage binary 'counter together with logic circuitry operating in conjunction with three diierent clock pulse sources for performing all necessary impulse recognition functions while utilizing a minimum number ot components.

Further objects, features, and advantages of the invention'wi'll become apparent as the following description proceeds, and the features of novelty which characterize the invention will be pointed out with particu- -larity in the claims annexed to andA forming a part or" this specic ation. g

For a better understanding of the invention, reference may be had to the accompanying drawings in which:

' FIG. l discloses a general schematic diagram of the environment or" the impulse analyzer of the present invention;

FIG. 2 discloses a pulsechart which is helpful in understanding the Yoperation 'of the disclosed embodiment of .he present invention; and V FIGS. 3A and 3B disclose a schematic of the preferred embodiment of the present invention. v

Referring now to FIG. l, one of a largeV number of line circuits ll is disclosed coupled to a vcom rnon trans- 3,l58,8l2 Patented Nov. 24, 1964 mission highwa l2 through a line gate i3. Line circuit iii is also disclosed coupled to a common transmission highway l2 through line gate 1d. It should be understood that a large number of line circuits are coupled to common transmission highway l2 in a time division multiplex switching system, which line circuits are not disclosed in FIP. 1. The impulse analyzer of the present invention may readily be utilized in the electronic switching system disclosed in application Serial No. 45,342 of Barrie Brightman, tiled luly 25, 1960 and assigned to the same assignee as the present invention. The impulse analyzer disposed the aforementioned application could be removed and the impulse analyzer of the present invention could be readily substituted. Of course, the se analyzer oi the present invention could be utilized in time division multiplex switching systems, or other systems, other than that disclosed in the aforementioned copending application. in that system, each line circuit is sequentially scanned to determine Whether or not service is being requested by a subscriber or machine associated with each individual line circuit. Let us assume that a ytelephone subscriber associated with line circuit lil desires to place a call. ln this case, he would lift the handset from the cradle, thus establishing an offhool; condition. Since all of the line circuits are sequential'ly scanned at high speeds for the purpose of detecting a request for service, in a few moments a time slot or impulse occurring once rduring each transmission framewould be applied to conductor ff of line ircuit 11. The ott-hook condition of the hoolswitch would result in contacts being closed so that a time slot pulse train would be applied to calling data bus l?, which is coupled to impulse analyzer l@ of the present invention. The subscriber subset coupled to line circuit Ill is capable of transmitting numerical pulse type directive information to the impulse analyzer. This mechanism forms no part of the present invention but will produce impulses, as disclosed in llG. 2, oi the numerical pulse type. The dial impulses, which will have a pulse width fof sixty milliseconds, are produced by causing hoolsswitch 16 to digit period, represented by B in FIG'. 2, which must be greater than one hundred milliseconds, occurs before the second digit is transmitted.

impulse analyzer l operating in conjunction with common control equipment@ after receiving the rst digit causes the digit to beinserted into a recirculating delay line memory store in binary form in common controlequipment i9. period E, show When the impulse analyzer recognizes in FlGYZ, as an interdigit period B vrather than an intradigit period, such as period H, a.A

steering circuit within common control equipment 19 is actuated so that the second digit, represented by impulse F in FIG. 2, does not affect the store which contains the rst digit but steers digit F into a lower order counter store. These digits are stored in a time slot within thev recirculating counter stores of common-control equipment l? in the same time slot as that assigned to line circuit 11.:

Aitor alll digitshave been;analyzed by "impulse, analyzer l and have been stored inthe appropriate recrrculatmg delay; line, counter ,store gates' are actuated so thatthe entire binaryfcoded decimal. number causes a particular' .cross-point` in a Vterminating line matrix to be enabled. 1

alessia the delay line module 315 after the cessation of the second impulse applied to conductor 369.

It should be apparent that after a minimum on-hook period of four milliseconds, a mark may be present on conductor 332 due to the presence of a time slot in delay line module 315. lt is possible that just after the occurrence of the leading edge A' of dial impulse A, disclosed in FIG. 2, an impulse is applied to conductor 369. Since this impulse will be repeated in four milliseconds, thereby to cause a time slot to be introduced into delay line module 315, as explained hereinabove, it follows that the interval between these two impulses will be at least four milliseconds.

As a result of the introduction of a time slot into delay line module 3l5, impulse gate 336 becomes partially enabled by virtue of the mark condition on lead 332. In `my case, an eight millisecond on-hook period will cause impulse gate 336 to be partially enabled.

lf the first dial impulse A, disclosed in FlG. 2, persists for at least four milliseconds, thereby to cause impulse gate 336 to become partially enabled, `a mark condition will be present on lead 337 since no time slot is contained within delay line module 338 owing to the fact that time slots are not present on calling data bus 391 during the on-hook period. This mark further enables impulse gate 336. Just after the occurrence of the trailing edge of first dial impulse A, of FIG. 2, a time slot pulse will be produced on calling data bus 331 which in turn produces a mark on lead 339, which mark passes through enabled impulse gate 335 and is forwarded to the aforementioned counter store which forms no part of the present invention. The second time slot which is applied to calling data bus 391 will not -be passed through impulse gate 336 thereby to give a spurious count since the rst time slot is emerging from delay line module 33S, thereby to cause a no mark condition to be produced on conductor 337, which in turn disena'oles impulse gate 335. The on-hook to off-hook condition, which is represented by the trailing edge of the lirst dial impulse A of FIG. 2, causes a no mark condition to be produced in the output circuit of detector 327 which disenables the AND gates contained within each delay line module of the counter, thereby to erase the recirculating time slots `and reset the counter. This erase condition is produced in the output circuit of detector 327 upon the occurrence of either the leading or trailing edges of the impulses shown in HG. 2 so that detector 327 may be described as a change of hook state detector. Since the impulse counter comprising delay line module 326 and delay Vline module 315 is utilized to measure the digit impulse, final ori-hook, and the interdigit period represented by B of FlG. 2, it is necessary that the counter be reset upon the occurrence of all leading and trailing edges of the pulse train of FlG. 2.

The hook-state detector 327 operates as follows. Upon the occurrence of the original oit-hook condition represented by C of FIG. 2, a time slot is produced upon calling data bus Sill, thereby to partially enable on-o gate 341 by virtue of conductor 342. Since this is the first time slot of a train of time slots to be impressed on calling data bus 301, a mark condition is present on output terminal B of delay line module 338 which causes a mark to be introduced into the input circuit of inverter 343 through OR gate 344. Consequently, the no mark erase condition, mentioned hereinabove, is produced on the input terminals F' .of the delay line modules of the impulse counter. 'l'he second time slot will not cause this erase condition because the lirst time slot will be emerging from delay line module 338 to disenable AND gate 341. During the interval when ori-o5 hook gate 341 is enabled, off-on gate 347 is disenabled due to the action of inverter 333.

Just after the occurrence of leading edge A of impulse A, which represents a change from the oil-hook to the on-hook condition, it follows that `a time slot will be produced -in the output circuit of delay line module 328 but that no time slot will be produced on calling data bus 3M so that conductor 342 at this time will not be marked so that on-ol gate 34l is disenabled. However, due to the action of inverter 303, off-on gate 347 becomes partially enabled so that the time slot produced on the output terminal A of delay line module 338 will pass through off-on gate 347 and OR gate 344, thereby to produce the aforementioned no mark erase condition in the output circuit of hook detector 327.

In summary, a no mark erase condition is produced in the output circuit of hook detector 327 upon each change of state of the hookswitch, which is manifested by either a cessation of the pulse train produced on calling data bus Sill or the generation of this train. Since the leading edge of the second digit impulse C, disclosed in FIG. 2, causes the counter to be reset, the aforementioned counting process is repeated so that an impulse is produced in the output circuit of impulse gate 336 in the event that impulse C has a minimum width of eight milliseconds.

Interdgz't Period Recognition Let us assume that the first digit is 3. In this case, the three impulses disclosed in FIG. 2 will be counted by the aforementioned counter store having its input circuit coupled to the output circuit of impulse gate 336. lf the second digit is 1, the impulse analyzer of the present invention rnust distinguish between interdigit periods, such as B shown in FlG. 2, and the forty rnillisecond period between impulses. In the absence of such a determination, thedial impulses of FlG. 2 would cause the digit 4 to be registered in the counter rather than the digits 3 and 1. ln order for the period B of FIG. 2 to be recognized by the impulse analyzer as an interdigit period, this period must be at least one hundred milliseconds in duration. Upon the occurrence of the trailing edge B', shown in FIG. 2, impulse sampling gates 39d and 305 are disenabled due to the action of inverter 3433. The negative-going time slots, however, are impressed upon co-nductor 3% but are unable to pass through disenabled impulse sampling gates 36d and 355. Sampling gate 367 is, however, partially enabled by a mark produced on conductor 35iL having the same time position in each transmission frame as the time slots present on conductor 366. This mark is produced by control storage circuitry, not shown, but described in the aforementioned copending application where some directive information is contained within the terminating line storage circuitry. Accordingly, at the beginning of period B, shown in FIG. 2, conductor 351 will be marked since the rst digit has been applied to the control storage circuitry. On the other hand, during the initial oit-hook period, labeled E in FIG. 2, no information would be stored in the control storage circuitry since no directive information has been transmitted. As a result, during the period labeled E, FIG. 2, conductor 35i would be unmarked to disenable AND gate 337. An impulse'having a pulse width of one hundred microseconds is applied to AND gate 367 via conductor 352 every one hundred milliseconds. During the period labeled B of FlG. 2, this impulse will pass through fully enabled AND gate 337 to cause a time slot to be inserted in delay line module 326, as previously explained. If the period labeled B is in fact an interdigit period, a second one hundred millisecond pulse will be passed'though AND gate 337 so as to insert a tirne slot in delay line module 315, as pre` Viously explained. One hundred microseconds later the A output terminal of delay line module 315 will be marked, thereby partially enabling end of digit gate 353 over conductor 357. Since a time slot train is applied to the calling data bus during this period, a time slot inpressed upon conductor 339 will pass through the enabled end of digit gate 353 to actuate the steering circuitry mentioned hereinabove. Since two one hundred millisecond impulses are required to pass through AND gate 337V to enabled end of digit gate 353, it follows that period B Y must be greater than one hundred vmilliseconds if the end of digit gate 353'is tol produce an output signal.

Should period B be less than one hundred milliseconds,

the leading edge or" the succeeding pulse would operate hook-state detector 327 to reset the counter, as previously explained, thereby to prevent the. actuation of end of digit gate 353.

Final Orl-.Hook

The impulse analyzer of the present invention must also be able to differentiate between a digit impulse, such as A, C, or F disclosed in FIG. 2, and a final' on-hookV condition, represented by G in' FIG. 2. lf the on-hook eondition is greater than one hundred and eight milliseconds, a final on-hook condition may be detest/ed but, ,in any case, fthe al oe-heekconditeu is greater-.than two hundred and four milliseconds, a finalen-hook condition will be detected. The impulse analyzer produces a mark in the' output CirouitV of inal on-.hook gate 361' Where the iinal oil-hook condition is detected. This signal is forwarded to the calling and terminating line stores, thereby to erase the time slot assigned to the call from these storage devices, and the call is accordingly released. At the beginning of the iinal on-hook period, the leading edge of impulse G of FIG. 2 causes the counter to be reset, as previously explained. Since the time slot train is not present on calling data bus 301 at this time, impulse sampling gate 307 is disenabled while AND gates304 and 305 are enabled owing to inverter 303. Accordingly, a four .millisecond mark is produced-on conductor 314 since module 315 is empty, to further enable AND gate 304' so that the four millisecond impulses present on conductor 309 willV pass through AND vgate 30.4,.thereby to insert a time slot into delay line module 326, as previously explained. The secondY four millisecondV impulse will cause a time slot to be inserted into delay line module 315 and will cause the time slot recirculating in delay line module 326 `to be erased. As a result, a no'mark condition is produced on conductor 314, thereby to disenable AND gate 394. The Vfirst one hundred millisecond impulse present on conductor 352 will pass through AND gate 395 and will cause a time slot to be inserted into delay-line module 326. One hundred microseconds later the mark is present on conductors 366 and 367, thereby to partially enable nal on-hook gate 361. Owing to n the absence of time slot impulses on calling data bus 301 and to the action of inverter .393, a mark is produced on conductor 367 which further enables linal on-hook gate 351'. However, at this time, the aforementioned one hundred millisecond impulse is no longer present on con- Y ductor 352 although this impulse was present one hundred Y to pass through AND gateil. An impulse will be producedrinY any case in the output circuit of nal on- A hook gate 361 vafter the occurrence of two-hundred and four milliseconds because, in the'worst case, the second VYtour millisecond impulse to bepassed by AND gate A394 would be coincident. with the tir-st one hundred millisecond impulse passed byAND gate Y305.` In this case, the

coincident secondy four millisecond impulse and the first one hundred millisecond impulse would merely register the second count so that a second and third one hundred millisecond impulse wouldbe necessary to count to four which is, of course, the required count to operate nal on-hookY gate 36l. Should. on-hook interval G be spurious and have a width of, say, fifty milliseconds, the onto Yoifhook conditionwoulcl be detected by hook detector 327 andthe impulse counter would be reset, as previously' i explained, to prevent the count of fou-r to be registered.

It vshould ber understood that the present invention is not restricted to' the Vparticular arrangement disclosed in FIGS. 3A and 3B. rangements are possible. For instance, let it be assumed that an output signalv is to be generated when a sixty rnillisecond pulse is applied to the analyzer.V This pulse Y gate may be provided having four input terminals, eachv coupledto ani output terminal of the first four stages of the binary counter. Accordingly, upon a count of sixteen, an output signal isv produced by the AND gate, thereby to indicate atv least a sixty millisecond interval.Y

The output signal produced by the AND gate may beV utilized toV operate steering circuitry similar to AND' gates 304, 305 and 307 of FIG. 3B. Accordingly, a one hundred millisecond pulse train, for instance, is now applied to the counter. A second AND gate is coupled to subsequent stages of thercounter, thereby to generate an output signal six-hundred milliseconds later, which output signal is produced when the count of six is added Vto the prior count of sixteen. Of course, the tolerance involved here would be plus or minus one hundred milliseconds Whereas the toleranceinvolved Where only the four millisecond pulse train is applied? would bev plus or minus' four milliseconds. It it is desired', further stages may be added to the counter and a third clock pulse source may have its output circuit steered to' the input circuit of the counter to measure lon-ger intervals.

While there has been disclosed what Vis at present conf Y sidered to be the preferred embodiment of the invention, other modilications will readily occur to those skilled in the art. It is not, therefore, desired that the invention be limited tothe speciiic arrangement shown and described .and it is intended in the appended claims to cover all such modications as fall within the true spirit Vandxscope of the invention.

What is claimed is: i

. l. n combination, a binary counter having a first and second stage, a iirst clock pulse source, a second clock pulse source for producing a lower frequency pulse Y than the pulse train produced by said iirst clock pulse source, al data source for producing a ii-rst orsecond con; dition, means responsive to said first condition for applying the pulses produced by said'iirst ,clock pulse source.-

to said binary counter, andmeans responsive to' the storage of a bit in` said secoud'.'stage` for preventing the application of the pulse train produced by said iirstV clock pulse to said binary counter and for causing the pulse train produced by saicl'secondV clock pulsel source to Vbe applied to said binaryicounter. f

2. The combination as set forth in claim 1 further in# cluding means coupled to said data source and responsive to the storage of a bit in both said first stage and said second stage for producing a first `control signal, provided Vthat saidiirst condition isV maintained during the counting process. j 1 Y 3. The combination as set forth in claim'l wherein meansr coupled to said data sourceare included forV producing a control signal when a bit is'sbored in said second stage, provided that a change occurs rom said iirst con:- dition to said second condition during the operation of said binary counter. i

4. The combination as set forth-in Vclaim` 21u/herein means coupled said data source areincluded yfor producinga second controi signal when a bit is stored in said secondV stage, provided that a change occurs between said In fact, an infinite number of ar- 3,1 9 first condition and said second condition during the operation of said binary counter.

5. .in combination, a binary counter having a rst and second stage, a iirst clock pulse source, a second clock puise source for producing a lower frequency pulse train than the pulse train produced by said first clock pulse source, a data source for producing a first or second condition, means responsive to said first condition for applying the pulses produced by said iirst clock pulse source to said binary counter, means responsive to the storage of a bit in said second stage for preventing the application of a pulse train produced by sm'd first clock pulse source to said binary counter and for causing the pulse train produced by said second clock pulse source to be applied to said binary counter, means responsive to said second condition for applying the pulses produced by said second clock pulse source to said binary counter whiie causing said counter to be reset, and means coupled to said data source for producing an output signal in response to tbe storage of a bit in said second stage provided that said second condition is maintained during the operation of said binary counter.

6. A circuit for indicating the commencement and cessation of a pulse train on a data bus comprising, a delay line having an input circuit coupled to said data bus, a irst and second AND gatereacb having a first and second input terminal, means for coupling the first input terminal of said first AND gate to the output circuit of said delay line, an inverter having an input and output circuit, means for coupling the input circuit of said inverter to said data bus, means for coupling the output circuit of said inverter to the second input terminal of said rst AND gate, means for coupling the iirst input terminal of said second ANB gate to said data bus, and means for inverting the output of said delay line and applying it to the second terminal of said second AND gate.

7. ln combination, a binary counter having a first and second stage, a lirst clock pulse source, a second clock asia pulse source for producing a lower frequency pulse train than the pulse train produced by said irst clock pulse source, a data source producing a iirst or second condition, means responsive to said iirst condition for applying the pulses produced by said first clock pulse source to said binary counter, means responsive to the storage of a bit in said second stage for preventing the application of the pulse train produced by said first clock pulse source to said binary counter and for causing the pulse train produced by said second clock pulse source to be applied to said binary counter, and means responsive to the storage of a bit in said first and second stages for producing an output signal unless said data source produces said second condition during the counting process and for a iixed period thereafter.

8. In combination, a binary counter having a plurality of stages, a rst clock pulse source, a second clock pulse source for producing a lower frequency pulse train than the pulse train produced by said iirst clock pulse source, a data source for producing a first or second condition, means responsive to said first condition for applying the pulses produced by said first clock pulse source to said binary counter, means responsive to the storage of a bit in certain of the stages of said counter for preventing the application of the pulse train produced by said first clock pulse source to said binary counter and for causing the pulse train produced by said second clock pulse source to be applied to said binary counter, and means responsive to the storage of bits in certain of the stages of said binary counter for producing an output signal, provided that said iirst condition is maintained during the counting process.

References Cited in the dle of this patent UNITED STATES PATENTS 2,656,106 Stabler Oct. 20, 1953 2,867,724 Olson Ian. 6, 1959 2,892,933 Shaw June 30, 1959 2,978,174 Dean et al Apr. 4, 1961 

1. IN COMBINATION, A BINARY COUNTER HAVING A FIRST AND SECOND STAGE, A FIRST CLOCK PULSE SOURCE, A SECOND CLOCK PULSE SOURCE FOR PRODUCING A LOWER FREQUENCY PULSE TRAIN THAN THE PULSE TRAIN PRODUCED BY SAID FIRST CLOCK PULSE SOURCE, A DATA SOURCE FOR PRODUCING A FIRST OR SECOND CONDITION, MEANS RESPONSIVE TO SAID FIRST CONDITION FOR APPLYING THE PULSES PRODUCED BY SAID FIRST CLOCK PULSE SOURCE TO SAID BINARY COUNTER, AND MEANS RESPONSIVE TO THE STORAGE OF A BIT IN SAID SECOND STAGE FOR PREVENTING THE APPLICATION OF THE PULSE TRAIN PRODUCED BY SAID FIRST CLOCK 